By G. Russell, I. Sayers
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Extra info for Advanced Simulation and Test Methodols for VLSI Design
3, the path through which source modifications influence the final design result can be very indirect, and it can be very hard to understand the effect of particular controls with respect to a specific design and tools methodology. Controls inserted early in the design flow might have a very different effect than desired or anticipated on the final result. A late fix in the design flow requires an enormous increase in manual design effort. Improving predictions has proven to be very difficult. Gain-based delay models traded off area predictability for significant delay predictability and gave some temporary relief, but in general it has been extremely hard to improve predictions.
How best to subpartition a design is a critical problem in EDA  and varies by application. For example, timing optimization may consider just critical timing paths, whereas area optimization may try to resize every cell that is not fixed. Portions of a design can be rapidly optimized in parallel in a distributed manner. Border constraints imposed to ensure consistency between workers’ changes to the design do reduce the optimality. Individual workers use sparse access to just read the portion of the design that they are optimizing, though logical connectivity may not be sufficient as cross-coupling analysis considers physically nearby wires.
2. Tools must be modular. 3. Tools must operate incrementally. Tools must sparsely access only the data that they need to reduce memory usage and runtime. Let us look at each of these in more detail in the following sections. 1 TOOL INTEGRATION Tool integration allows them to directly communicate with each other. A superficial form of integration can be provided by initiating, from a common user interface, the execution of traditional point tools that read input from files and save output to files.
Advanced Simulation and Test Methodols for VLSI Design by G. Russell, I. Sayers